/*
*
*
*     文档创建：jjl, jjl@hzncc.com
*/


module rmii_connector(
            sys_clk         ,
            sys_reset_n     ,
            
            //phy0
            phy0_rxdv       ,
            phy0_rxd        ,
            phy0_txen       ,
            phy0_txd        ,

            //phy1
            phy1_rxdv       ,
            phy1_rxd        ,
            phy1_txen       ,
            phy1_txd        ,

 
            //报文处理逻辑
            rxdv            ,
            rxd             ,
            txen            ,
            txd             
        );

    input wire              sys_clk         ;
    input wire              sys_reset_n     ;

    //PHY0
    input wire              phy0_rxdv       ;
    input wire      [1:0]   phy0_rxd        ;
    output logic            phy0_txen       ;
    output logic    [1:0]   phy0_txd        ;

    //PHY1
    input wire              phy1_rxdv       ;
    input wire      [1:0]   phy1_rxd        ;
    output logic            phy1_txen       ;
    output logic    [1:0]   phy1_txd        ;

    //报文处理接口
    output logic            rxdv            ;
    output logic    [1:0]   rxd             ;
    input wire              txen            ;
    input wire      [1:0]   txd             ;

    //对于PHY0 RX --> 报文处理的RX
    logic                   phy0_rxdv_r     ;
    logic       [1:0]       phy0_rxd_r      ;
    logic                   phy0_rxdv_rr    ;
    logic       [1:0]       phy0_rxd_rr     ;
    always_ff@(posedge sys_clk or negedge sys_reset_n)
    if(~sys_reset_n)    begin
        phy0_rxdv_r     <=      '0          ;
        phy0_rxd_r      <=      '0          ;
        phy0_rxdv_rr    <=      '0          ;
        phy0_rxd_rr     <=      '0          ;
        rxdv            <=      '0          ;
        rxd             <=      '0          ;
    end else begin
        phy0_rxdv_r     <=      phy0_rxdv   ;
        phy0_rxd_r      <=      phy0_rxd    ;
        phy0_rxdv_rr    <=      phy0_rxdv_r ;
        phy0_rxd_rr     <=      phy0_rxd_r  ;
        rxd             <=      phy0_rxd_rr ;
        if(~(phy0_rxdv_rr ^  phy0_rxdv_r))  //如果两拍不等，保持
            rxdv        <=      phy0_rxdv_rr;
    end

    //对于PHY0的TX-->PHY1的RX
    logic                   phy1_rxdv_r     ;
    logic       [1:0]       phy1_rxd_r      ;
    logic                   phy1_rxdv_rr    ;
    logic       [1:0]       phy1_rxd_rr     ;
    always_ff@(posedge sys_clk or negedge sys_reset_n)
    if(~sys_reset_n)    begin
        phy1_rxdv_r     <=      '0          ;
        phy1_rxd_r      <=      '0          ;
        phy1_rxdv_rr    <=      '0          ;
        phy1_rxd_rr     <=      '0          ;
        phy0_txen       <=      '0          ;
        phy0_txd        <=      '0          ;
    end else begin
        phy1_rxdv_r     <=      phy1_rxdv   ;
        phy1_rxd_r      <=      phy1_rxd    ;
        phy1_rxdv_rr    <=      phy1_rxdv_r ;
        phy1_rxd_rr     <=      phy1_rxd_r  ;
        phy0_txd        <=      phy1_rxd_rr ;
        if(~(phy1_rxdv_rr ^ phy1_rxdv_r))
            phy0_txen   <=      phy1_rxdv_rr ;
    end

    //对于报文处理的TX-->PHY1的TX
    logic                   phy1_txen_r     ;
    logic       [1:0]       phy1_txd_r      ;
    always_ff@(posedge sys_clk or negedge sys_reset_n)
    if(~sys_reset_n)    begin
        phy1_txen_r     <=      '0          ;
        phy1_txd_r      <=      '0          ;
    end else begin
        phy1_txen_r     <=      txen        ;
        phy1_txd_r      <=      txd         ;
        phy1_txen       <=      phy1_txen_r ;
        phy1_txd        <=      phy1_txd_r  ;
    end

endmodule
